[BUG]Safety classifier false-positive on formal verification / EDA work

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• [x] I have searched existing issues and this hasn't been reported yet
• [x] This is a single bug report (please file separate reports for different bugs)
• [x] I am using the latest version of Claude Code

What's Wrong?

While doing standard pre-silicon hardware verification -- running Cadence JasperGold formal proofs on an ARM CMN (Coherent Mesh Network) interconnect design -- a message was flagged as if it were offensive-security/exploit work. This is legitimate design verification engineering (SVA properties, bind-in checkers, counterexample triage), not cybersecurity exploitation. Please tune the classifier to distinguish formal verification / EDA tooling (JasperGold, Xcelium, SVA, UVM, bind checkers, mesh/AXI protocol properties) from actual exploit development.

What Should Happen?

The classifier should recognize formal hardware verification and EDA tooling as legitimate engineering, not offensive security. Running Cadence JasperGold to prove SVA/UVM properties on an ARM CMN interconnect (bind-in checkers, counterexample triage, protocol/credit/FIFO assertions) is standard pre-silicon design verification and should not be flagged. It should distinguish this from actual exploit development -- signals like JasperGold/Xcelium/VCS, SVA/assert property/assume property, UVM, bind checkers, AXI/CHI/mesh protocol properties, and RTL filelists (.f/.tcl) indicate DV work, whereas exploit development involves attacking deployed systems, crafting shellcode/payloads, or evading defenses. The verification session should proceed without a security flag.

Error Messages/Logs

Fable 5's safeguards flagged this message. The safeguards are intentionally broad right 
  now and may flag safe and routine coding, cybersecurity, or biology work. These measures 
  let us bring you Mythos-level capabilities sooner, and we're working to refine them. 
  Switched to Opus 4.8. Send feedback with /feedback or learn more

Steps to Reproduce

1. In Claude Code, work on standard pre-silicon hardware verification of an ARM CMN Coherent Mesh Network) interconnect.
2. Use Cadence JasperGold for formal verification -- author SVA properties and bind-in checkers (assert property / assume property / cover), run jg -batch, and triage counterexamples (e.g., FIFO overflow, credit-protocol, AXI/CHI mesh protocol assertions).
3. Ask the model to help write/run these formal checkers and analyze the results (e.g., a virtual-queue overflow property, a bank-collision write-delivery theorem, a metadata-ordering fence).
4. Observe: a message in this formal-verification workflow is flagged as if it were offensive-security / exploit-development content.

Expected: the formal verification / EDA work is recognized as legitimate design verification and not flagged.
Actual: the safety classifier false-positives on the DV / JasperGold activity.

Environment: Claude Code (model: Fable 5); Cadence JasperGold formal verification;
SystemVerilog/UVM/SVA; ARM CMN interconnect RTL. No exploit development, no targeting of
any deployed system -- pre-silicon design verification only.

Claude Model

Other

Is this a regression?

Yes, this worked in a previous version

Last Working Version

_No response_

Claude Code Version

2.1.214 (Claude Code)

Platform

Anthropic API

Operating System

Ubuntu/Debian Linux

Terminal/Shell

Xterm

Additional Information

_No response_